1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for forming wells of a semiconductor device which are proper for the high integration of a semiconductor device.
2. Description of the Prior Art
Referring to FIG. 1, a conventional method for forming profiled wells of a semiconductor device is illustrated. FIG. 1 is a sectional view explaining the conventional well forming method. Incontrast, FIG. 2 is a graph depicting an impurity ion concentration distribution depending on a well depth in the structure of FIG. 1.
In accordance with the conventional method, an element-isolating film 2 is formed over a semiconductor substrate 1, as shown in FIG. 1. Using a high energy ion implanting device, a well ion implanted layer 3, a channel stop ion implanted layer 4 and a threshold voltage ion implanted layer 5 are then sequentially formed in the semiconductor substrate 1.
After the formation of the implanted layers, vacancy dot defects (not shown) are distributed in a portion of the semiconductor substrate 1 extending up to about 0.8 Rp from the surface of the semiconductor substrate 1. Here, "Rp" means a projected range determined by ion implantation energy. Interstitial dot defects are also distributed in a portion of the semiconductor substrate 1 ranging from 1 to 2 Rp.
Thereafter, the resulting structure is annealed in a furnace, which is maintained at a temperature of about 900 to 1,000.degree. C. for about one hour, thereby electrically activating the dopants. Thus, a profiled well is formed.
In contrast, FIG. 2 shows an impurity ion concentration distribution and defect distribution in the semiconductor substrate depending on the depth of the semiconductor substrate. In FIG. 2, the curve 11 depicts an impurity ion concentration distribution in the well, the curve 12 depicts an impurity ion concentration distribution upon the channel stop ion implantation. The curve 13 depicts an impurity ion concentration distribution in the ion implantation for a threshold voltage control. The curve 14 depicts an interstitial dot defect distribution. The curve 15 depicts a vacancy dot defect distribution.
Referring to FIG. 2, the channel step ion implanted region and the ion implanted region for forming the well have a large space differential in accordance with the conventional method. As a result, the dot defects existing in the interstitial dot defect layer formed upon the channel step ion implantation can not be coupled with the dot defects existing in the vacancy dot defect layer formed upon the ion implantation for forming the well when a subsequent thermal annealing is carried out. As a result, such dot defects are left after the subsequent thermal annealing. Furthermore, an increase in resistance occurs because no dopant exists between the two ion implanted layers.
In order to eliminate the above-mentioned defects, a thermal annealing should be conducted at a high temperature for a long time. However, in this case, diffusion of dopants occurs, thereby resulting in a variation in the ion concentration distribution. Consequently, a degradation in the characteristic of the well occurs.
As is apparent from the above description, the conventional well forming method involves a degradation in the electrical characteristic of the semiconductor device which is eventually produced. This results in the degraded reliability of the semiconductor device. Consequently, the conventional method is improper for the high integration of semiconductor devices.